1. Field of the Invention
The present invention relates to a mask pattern formed on a photomask, a pattern formed on a semiconductor device, and a method for exposing through the photomask to form a resist pattern of which a position is employed to correct an exposure condition.
In the present specification, an overlay error measuring mark formed on the photomask will specifically be referred to as an on-mask photolithography screening mark and the mark transferred onto or formed on a resist layer or a semiconductor substrate in order to determine the amount of pattern displacement will be referred to as a photolithography screening mark.
2. Description of the Related Art
Size reduction of a semiconductor device has been achieved by reducing the size of each component. In addition to this, since the semiconductor device is composed of a plurality of circuit layers, contact holes and the other elements, it is also an important technique in view of size reduction to improve the overlay accuracy for various elements.
A series of processes such as layer formation, photolithography operation and etching to form the elements in the manufacture of the semiconductor device will hereafter collectively be referred to as a xe2x80x9cmanufacturing processxe2x80x9d. A semiconductor device is typically manufactured by a plurality of manufacturing processes. When a patterned first circuit layer is formed on a semiconductor substrate and then a second patterned circuit layer is to be formed on the first circuit layer, the second circuit layer is blanket deposited on the first circuit layer, and then a resist layer is formed on the second circuit layer. The resist layer is then exposed to light through a photomask that includes a pattern corresponding to a pattern of the second circuit layer to form a resist pattern.
The photomask has various patterns formed thereon in correspondence to the circuit and other patterns formed on the semiconductor substrate. By exposing the resist layer to light through the pattern formed on the photomask (namely exposure), a pattern that is ideally a similar figure to the photomask pattern is formed on the resist layer. Actually, however, a displacement between a designed pattern of the second circuit layer corresponding to the pattern of the first circuit layer and the resulting resist pattern may occur due to optical conditions such as optical aberration through an optical system in the exposure apparatus. When the pattern of the second circuit layer is etched by using a resist pattern that has a displacement, the resulting pattern of the second circuit layer also includes a displacement from a designed position. The displacement of the resist pattern is usually called the overlay displacement.
There have been various marks used in the photolithography processes to measure various data related to the photolithography. In this specification, these marks will all be called the measurement mark.
In order to measure the amount of the overlay displacement, for example, a mark called an alignment mark is formed on the photomask or transferred with the photomask on the semiconductor substrate. This is also a kind of the measurement mark described above.
Among the overlay displacements, one which is determined using the alignment mark formed on the photomask and the alignment mark actually formed in the resist pattern is called a position error. Moreover, when a pattern (such as a line in a circuit and a contact hole) is formed on the semiconductor substrate using a resist pattern that includes the position error, a deviation in the dimension or the shape from the ideal pattern of similar shape is produced. This is called a patterning error.
The smaller the element dimensions the smaller the tolerance for overlay displacement caused by the effect of optical aberration on the optical system in the exposure apparatus.
Specifically, the position error due to frame aberration as a type of optical aberration is described for example in Japanese Kokai Patent Publication No. Hei 9 (1997)-74063, especially in the description referring to FIGS. 59 to 61.
As a technique for reducing the position error, Japanese Kokai Patent Publication Nos. Hei 9 (1997)-74063 and Hei 9 (1997)-244222 propose technologies for improving the measurement mark used to relatively determine the position error such as the alignment mark.
However, even when the measurement mark is improved according to the description in the publications mentioned hereinbefore, the following problems are expected to occur when the element sizes are further reduced.
The first problem is that since the value of overlay displacement determined by using the conventional measurement mark is a relative position error of the pattern formed in the subsequent manufacturing process to the pattern formed in the previous manufacturing process, it is not possible to determine merely the actual position error of the pattern obtained in the subsequent manufacturing process.
Particularly, since the position error may block further reduction of element sizes, it is required to accurately determine the amount of the position error.
The second problem refers to the difficulty of analyzing the overlay displacement.
In the prior art, for example, when a relative position error is larger than a limit value after completing a plurality of manufacturing processes, a main cause of the error has been attributed to a downstream manufacturing process because the value of position error generated in the downstream manufacturing process is normally larger than one generated in an upstream manufacturing process. In the prior art, however, it has been difficult to determine which of a upstream or a downstream manufacturing process has greater contribution to the final position error in actuality.
The present invention has been made to solve the problems described above, and a first object thereof is to provide a photomask and a semiconductor device that allow it to accurately determine the actual position error and the patterning error separately for each manufacturing process.
Second object of the present invention is to provide a semiconductor device having higher precision and a less patterning error.
Third object of the present invention is to provide an exposure method comprising the correction of exposure conditions based on the resulting position error data.
The photomask according to the first aspect of the present invention comprises a photomask substrate, and an on-mask circuit area including an on-mask circuit pattern and an on-mask test mark area including an on-mask test pattern, both formed on the surface of the substrate, wherein the photomask substrate further includes an on-mask photolithography screening mark area including an on-mask comparison pattern and an on-mask screening pattern, the on-mask comparison pattern has substantially the same configuration as at least a part of the on-mask circuit pattern, and the on-mask screening pattern has substantially the same configuration as at least a part of the on-mask test pattern.
According to the present invention, the photomask has the on-mask comparison pattern and the on-mask screening pattern disposed close to each other.
According to the present invention, either one of the on-mask comparison pattern or the on-mask screening pattern is disposed at both ends of the other.
According to the present invention, either one of the on-mask comparison pattern or the on-mask screening pattern is disposed to surround the other.
According to the present invention, the on-mask comparison pattern and the on-mask screening pattern combine to form a cross-shaped mark on the photomask.
According to the present invention, either one of the on-mask photolithography screening mark area or the on-mask test mark area is included in the other, and the on-mask test pattern further serves as the on-mask screening pattern.
According to the present invention, the photomask may have a plurality of the on-mask photolithography screening mark areas and arrangement thereof may be at any position.
Second aspect of the present invention is a semiconductor device comprising a semiconductor substrate having a circuit area including circuit patterns and a measurement mark area including measurement patterns formed on the surface of the semiconductor substrate in the same manufacturing process as the circuit pattern, wherein the semiconductor substrate further includes a photolithography screening mark area including a screening pattern.and a comparison pattern, the comparison pattern has substantially the same configuration as at least a part of the circuit pattern, and the screening pattern has substantially the same configuration as at least a part of the the measurement pattern.
In the semiconductor device according to the present invention, the screening pattern and the comparison pattern are disposed close to each other in the same manufacturing process.
According to the present invention, second model of a semiconductor device comprises a semiconductor substrate, and a plurality of photolithography screening mark areas including a screening pattern formed on the surface of the semiconductor substrate, wherein the photolithography screening mark area further includes a comparison pattern formed in the same manufacturing process as the screening pattern to be close thereto, and a dimensional difference between the screening patterns having the same configuration and the same dimensions included in different photolithography screening mark areas equals to a dimensional difference between the comparison-patterns of the same configuration and the same dimensions included in the photolithography screening mark areas. In this semiconductor device, the screening pattern and the comparison pattern are disposed close to each other.
According to the present invention, third model of a semiconductor device comprises a semiconductor substrate manufactured by employing a photolithography process using a photomask comprising a photomask substrate, and an on-mask circuit areas including on-mask circuit patterns, an on-mask test mark area including on-mask test patterns and an on-mask photolithography-screening mark area including an on-mask comparison pattern and an on-mask screening pattern, all of them formed on the surface of the substrate, wherein the on-mask comparison pattern has substantially the same configuration as at least a part of the on-mask circuit pattern, and the on-mask screening pattern has substantially the same configuration as at least a part of the on-mask test pattern, whereby a plurality of photolithography screening mark areas corresponding to the on-mask photolithography screening mark areas, including a screening pattern corresponding to the on-mask screening pattern and a comparison pattern corresponding to the on-mask comparison pattern formed on the surface of the semiconductor substrate, a dimensional difference between the screening patterns having the same configuration and the same dimensions included in different photolithography screening mark areas, respectively, equals to a dimensional difference between the comparison patterns of the same configuration and the same dimensions included in the photolithography screening mark areas.
In the present invention, the photomask comprises the on-mask screening pattern and the on-mask comparison pattern, both disposed close to each other.
According to the semiconductor device of the present invention, either one of the screening pattern or the comparison pattern is disposed at both ends of the other.
According to the semiconductor device of the present invention, either one of the screening pattern or the comparison pattern is disposed to surround the other.
According to the semiconductor device of the present invention, the screening pattern and the comparison pattern combine to form a cross-shaped mark.
In the semiconductor device according to the present invention, either one of the photolithography screening mark area and the measurement mark area may be included in the other, and the measurement pattern may have the function of the screening pattern as well.
In the semiconductor device according to the present invention, the photolithography screening mark area may be included in plurality and arrangement thereof may be at any position.
An exposure method according to another aspect of the present invention uses an exposure apparatus equipped with a photomask, comprising:
(i) a step of exposing a resist layer formed on a surface of a semiconductor substrate to light on the exposure apparatus equipped with the photomask comprising a photomask substrate, and an on-mask circuit area including on-mask circuit patterns, an on-mask test mark area including on-mask test patterns and an on-mask photolithography screening mark area including an on-mask comparison pattern and an on-mask screening pattern, all of them formed on the surface of the substrate, wherein the on-mask comparison pattern has substantially the same configuration as at least a part of the on-mask circuit pattern, and the on-mask screening pattern has substantially the same configuration as at least a part of the on-mask test pattern, thereby to form an on-resist circuit area that correspond to the on-mask circuit area, on-resist circuit patterns that correspond to the on-mask circuit patterns, an on-resist test-mark area that correspond to the on-mask test mark area, on-resist test patterns that correspond to the on-mask test patterns, an on-resist photolithography screening mark area that correspond to the on-mask photolithography screening mark area, an on-resist screening pattern that correspond to the on-mask screening pattern, and an on-resist comparison pattern that correspond to the on-mask comparison pattern on the resist layer; and
(ii) a step of correcting the exposure conditions based on a position error data obtained by measuring a distance between the on-resist screening pattern and the on-resist comparison pattern.
On the photomask used-in the method of the present invention, the on-mask comparison pattern and the on-mask screening pattern are disposed close to each other.
According to the exposure method of the present invention, either one of the on-mask photolithography screening mark area or the on-mask test mark area is included in the other, and the on-mask test pattern further serves as the on-mask screening pattern.